`include "C:\Users\lenovo\Desktop\Files\Linear_RISCV\LR_ver_0\src\include\include.vh"
module 	DMEM_ctrl(
    input         [2: 0]  Load_sel_exu,
    input         [10:0]      exu_high,
    input         [63:0]   Dmem_R_Data,
    output reg    [63:0]     Dmem_Addr,
    output reg    [63:0]     Load_data
);
    always@(*) begin
        case(Load_sel_exu)
            `LB:
                begin
                    case(exu_high[2:0])
                        3'b000:Load_data={{56{Dmem_R_Data[7]}},Dmem_R_Data[7:0]};
                        3'b001:Load_data={{56{Dmem_R_Data[15]}},Dmem_R_Data[15:8]};
                        3'b010:Load_data={{56{Dmem_R_Data[23]}},Dmem_R_Data[23:16]};
                        3'b011:Load_data={{56{Dmem_R_Data[31]}},Dmem_R_Data[31:24]};
                        3'b100:Load_data={{56{Dmem_R_Data[39]}},Dmem_R_Data[39:32]};
                        3'b101:Load_data={{56{Dmem_R_Data[47]}},Dmem_R_Data[47:40]};
                        3'b110:Load_data={{56{Dmem_R_Data[55]}},Dmem_R_Data[55:48]};
                        3'b111:Load_data={{56{Dmem_R_Data[63]}},Dmem_R_Data[63:56]};
                    endcase
                end
            `LBU:
                begin
                    case(exu_high[2:0])
                        3'b000:Load_data={56'b0 ,Dmem_R_Data[7:0]};
                        3'b001:Load_data={56'b0,Dmem_R_Data[15:8]};
                        3'b010:Load_data={56'b0,Dmem_R_Data[23:16]};
                        3'b011:Load_data={56'b0,Dmem_R_Data[31:24]};
                        3'b100:Load_data={56'b0,Dmem_R_Data[39:32]};
                        3'b101:Load_data={56'b0,Dmem_R_Data[47:40]};
                        3'b110:Load_data={56'b0,Dmem_R_Data[55:48]};
                        3'b111:Load_data={56'b0,Dmem_R_Data[63:56]};
                    endcase
                end
            `LH:
                begin
                    case(exu_high[1:0])
                        2'b00:Load_data={{48{Dmem_R_Data[15]}},Dmem_R_Data[15:0]};
                        2'b01:Load_data={{48{Dmem_R_Data[31]}},Dmem_R_Data[31:16]};
                        2'b10:Load_data={{48{Dmem_R_Data[47]}},Dmem_R_Data[47:32]};
                        2'b11:Load_data={{48{Dmem_R_Data[63]}},Dmem_R_Data[63:48]};
                    endcase
                end
            `LHU:
                begin
                    case(exu_high[1:0])
                        2'b00:Load_data={48'b0,Dmem_R_Data[15:0]};
                        2'b01:Load_data={48'b0,Dmem_R_Data[31:16]};
                        2'b10:Load_data={48'b0,Dmem_R_Data[47:32]};
                        2'b11:Load_data={48'b0,Dmem_R_Data[63:48]};                       
                    endcase
                end
            `LW:    Load_data={{32{Dmem_R_Data[31]}},Dmem_R_Data[31:0]};
            `LWU:   Load_data={32'b0,Dmem_R_Data[31:0]};
            `LD:    Load_data=Dmem_R_Data;                                 
            default: Load_data=`REGD_ZERO;
        endcase
    end
    always@(*) begin
        case(Load_sel_exu)
            `LB:    Dmem_Addr=exu_high[10:3];
            `LBU:   Dmem_Addr=exu_high[10:3];
            `LH:    Dmem_Addr=exu_high[9:2];
            `LHU:   Dmem_Addr=exu_high[9:2];
            `LW:    Dmem_Addr=exu_high[8:1];
            `LWU:   Dmem_Addr=exu_high[8:1];
            `LD:    Dmem_Addr=exu_high[7:0];                                                             
            default: Dmem_Addr=`REGD_ZERO;
        endcase
    end
endmodule